Sonifex Software
RB-VHDMA8, RB-VHEMA8, RB-VHCMA4 & RB-VHCMD16 Firmware Versions
Versions for units running V2.X.X
Firmware V2.1.3 / FPGA V2.1.0
- Firmware
- Added support for updated component.
Firmware V2.1.1 / FPGA V2.1.0
- Firmware
- Fixed bug with setting of channel status for the analog inputs
- Fixed channel mapping bug for the channel status info
Firmware V2.1.0 / FPGA V2.1.0
- Firmware/FPGA
- Added a new option - Embed insert allows inserting channels to existing groups.
Firmware V2.0.5 / FPGA V2.0.4
- Firmware
- Fixed bug with reading setting of control mode on startup.
Firmware V2.0.4 / FPGA V2.0.4
- Firmware
- Added front panel lock persistance option.
- Front panel lock now settable through front panel - (press and hold bank channel, group channel and status buttons for 5 seconds).
Firmware V2.0.2 / FPGA V2.0.4
- Firmware
- Reduced default front panel LED brightness slightly
- Added front panel brightness control via remote control
- When the SRC is disabled for an input and the input loses lock, the audio output would sometimes freeze at the last sample level. This has been fixed
- Added optimized internet checksum routine
- Fixed bug in video delay control
- FPGA
- Increased delay width to allow for SD line delay
Firmware V2.0.1 / FPGA V2.0.3
- Initial release
Versions for units running V0.X.X
Firmware V0.4.0 / FPGA V0.3.0
- Firmware
- Updated drivers to latest versions.
- Added front panel lock persistance option.
- Front panel lock now settable through front panel - (press and hold bank channel, group channel and status buttons for 5 seconds).
- FPGA
- Updated soft core components to latest versions.
Firmware V0.3.6
- Fixed fatal error when updating units due to incorrect memory mapping.
- Fixed issue with intialising AIM-AD daughter boards.
Firmware V0.3.5
- Reduced default front panel LED brightness slightly
- Added front panel brightness control via remote control
- When the SRC is disabled for an input and the input loses lock, the audio output would sometimes freeze at the last sample level. This has been fixed
Firmware V0.3.4 / FPGA V0.2.9
- Firmware
- Added new driver for new revision AIM-DD card with selectable termination.
- FPGA
- Fixed de-embed routing error.
FPGA V0.2.7
- Fixed audio routing error introduced in version 0.2.6.
Firmware V0.3.1 / FPGA V0.2.6
- Firmware
- Reverted default IP address back to 192.168.0.100 and gateway to 192.168.0.1 to remain standard with other units
- FPGA
- Fixed bug where HD Luma/Chroma streams would sometimes become misaligned during locking.
FPGA V0.2.4/5
- Internal versions. Not released.
Firmware V0.3.0 / FPGA V0.2.3
- Firmware
- Now allows multiple connections over TCP/IP.
- New command RWC; Requests write permission (RS-232 always has write permission).
- New command WAL; Changes "login" details for write permission.
- New command GAC; Retrieves current "admin" connection(s).
- Updated TCP/IP stack.
- Improved message handling from UART, TCP and UDP connections.
- Changed default IP address to 192.168.1.2 and gateway to 192.168.1.1.
- Changed command CLR; Resets login details to defaults.
- Can no longer press+hold the bank channel button while in bank mode.
- Improved FPGA/firmware update process.
- Channel status is no longer continously read/written when digital I/O sub-boards are fitted. Changes in the data are detected and written in a round robin sequence.
- Other minor improvements.
- FPGA
- Channel status for channels 2 and 4 in a group are now de-embedded correctly into RAM.
Firmware V0.2.1 / FPGA V0.2.2
- FPGA
- Corrected clock phase information for HD audio packets.
Firmware V0.2.1 / FPGA V0.2.1
- FPGA
- Corrected parity bit in SD audio packets.
Firmware V0.2.1 / FPGA V0.2.0
- Firmware
- Rebuild for new CPU soft core, with updated drivers.
- SDI locking improved.
- Fixed SCId memory leak.
- Other minor changes/fixes.
- FPGA
- Corrected data block numbering in audio packets.
- New CPU soft core version.
- SDI locking improved.
Firmware V0.1.8 / FPGA V0.1.1
- Initial release
